Fordham, New York City's Jesuit University
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FORDHAM UNIVERSITY CSLU 3593
Fordham College Lincoln Center Computer Organization
Dept. of Computer and Info. Science Spring, 2005



Homework Assignment 8
Due date: April 21

5.1
[11] $<$§5.2$>$ Do we need combinational logic, sequential logic, or a combination of the two to implement each of the following:
  1. multiplexor
  2. comparator
  3. incrementer/decrementer
  4. barrel shifter (a device which shifts an input word right or left by a specified number of bits)
  5. multiplier implemented with shifters and adders (Figure 3.9)
  6. register
  7. memory
  8. ALU (the ones in single-cycle and multiple-cycle datapaths)
  9. carry look-ahead adder (see Section B.6)
  10. latch
  11. general finite state machine (FSM)

5.8
[15] $<$§5.4$>$ We wish to add the instruction jr (jump register) to the single-cycle datapath described in this chapter. (This instruction is described on p. 76.) Add any necessary datapaths and control signals to the single-cycle datapath of Figure 5.17 on page 307 and show the necessary additions to Figure 5.18 on page 308. You can photocopy these figures to make it faster to show the additions.

5.10
[15] $<$§5.4$>$ This question is similar to Exercise 5.8 except that we wish to add the instruction lui (load upper immediate), which is described in section 2.9.

5.11a
[5] $<$§§2.3,5.4$>$ The text's Exercise 5.11 proposes a variant of the lw instruction called l_inc that increments the index register after loading the word from memory. This instruction is defined to correspond to the two MIPS instructions

$\textstyle \parbox{3in}{%
{\tt lw\ \ \ \$rs, L(\$rt)} \\
{\tt addi \$rt, \$rt, 1}}$

The l_inc instruction would not be very useful if it were implemented in this way. Explain why and correct the definition in a way that would be more useful.


Robert Moniot 2005-04-07