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FORDHAM UNIVERSITY CSLU 3593
Fordham College Lincoln Center Computer Organization
Dept. of Computer and Info. Science Spring, 2005

Homework Assignment 9
Due date: April 28

4.10

[20] $<$§4.2$>$ Consider two different implementations, I1 and I2, of the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set. Machine I1 has a clock rate of 6 GHz, and I2 has a clock rate of 3 GHz. The average number of cycles for each instruction class on I1 and I2 is given by the following table:

Class	CPI on I1	CPI on I2	C1 Usage	C2 Usage	C3 Usage
A	2	1	40%	40%	60%
B	3	2	40%	20%	15%
C	5	2	20%	40%	25%

The table also contains a summary of the average proportions of instruction classes executed in the code generated by three different compilers. C1 is a compiler produced by the makers of I1, C2 is produced by the makers of I2, and the other compiler is a third-party product. [Note that the figures for C3 in this table differ from those in some printings of the text.] Assume that each compiler uses the same number of instructions for a given program but that the instruction mix is as described in the table.

1. Using C1 on both I1 and I2, how much faster can the makers of I1 claim I1 is compared to I2?
2. Using C2, how much faster can the makers of I2 claim that I2 is compared to I1?
3. If you purchased I1, which compiler would you use?
4. If you purchased I2, which compiler would you use?
5. Which computer and compiler would you purchase if all other criteria are identical, including cost?

Justify each of your answers.

5.13

[10] $<$§5.4$>$ Consider the single-cycle datapath in Figure 5.17. A friend is proposing to modify this single-cycle datapath by eliminating the control signal MemtoReg. The multiplexor that has MemtoReg as an input will instead use either the ALUSrc or the MemRead control signal. Will your friend's modification work? Can one of the two signals (MemRead and ALUSrc) substitute for the other (MemtoReg)? Explain. If this plan would work, what might be a reason for keeping MemtoReg anyway?

5.14

[10] $<$§5.4$>$ The MIPS design philosophy chooses to simplify the structure of its instructions. Instead of implementing complex instructions in hardware, we decompose them into multiple simpler MIPS instructions. Show how to implement the instruction swap $rs, $rt, which swaps the contents of registers $rs and $rt, using a sequence of MIPS instructions. These instructions may use the $at register as a temporary register whose contents can be destroyed. Use only actual MIPS instructions, not pseudo-instructions.

If the implementation of this instruction in hardware will increase the clock period of a single-cycle implementation by 10%, what percentage of swap operations in the instruction mix would recommend implementing it in hardware? (If implemented in hardware, a swap would take only 1 clock cycle, whereas if implemented as above it would take 3 clock cycles.)

For 5 points extra credit, find a way to implement the swap instruction in MIPS without destroying the contents of any third register or using memory. Hint: it can be done in the same number of instructions as the implementation that uses a third register.