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§5.5
We wish to add the instruction
lui (load upper immediate) described in section 2.9 to the
multicycle datapath described in this chapter. Augment the
multicycle datapath of Figure 5.28 on page 323 with any necessary
additions and show the necessary modifications to the finite state
machine of Figure 5.38 on page 339. (You may photocopy the figures
to make it easier to show the changes.) Describe in detail what
happens on each clock cycle (i.e. as was done for the other
instructions on pp. 325-329 of the text). Try to make the
instruction take the fewest possible cycles to complete.
§5.5 This question is like 5.32,
except that we wish to implement the jr (jump register)
instruction, which causes a jump to the address contained in the
register specified by the rs field of the instruction.
§5.5 Your friends at 
(Creative Computer Corporation) have determined that the critical
path that sets the clock cycle length of the multicycle datapath is
memory access for loads and stores (not for fetching instructions).
This has caused their newest implementation of the MIPS 30000 to run
at a clock rate of 4.8 GHz rather than the target clock rate of 5.6
GHz. However, Clara at has a solution. If all the
cycles that access data memory are broken into two clock cycles,
then the machine can run at its target clock rate. (On the FSM diagram,
each node corresponding to a data memory access becomes two nodes
with the same set of outputs, with one node transitioning to the
next before continuing to the next operation.)
Assume the following mix of instruction types: load 26%, store 10%, register-register 49%, branch/jump 15%. Determine how much faster the 5.6 GHz machine with the two-cycle memory accesses is compared with the 4.8 GHz machine with the single-cycle memory accesses.
Suppose that splitting the instruction fetch step into two cycles would allow a further increase of the clock speed to 6.4 GHz. Would this increase the performance of the machine even further, and if so by how much?